This application claims the benefit of the Korean Application No. P2001-71841 filed on Nov. 19, 2001, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a nonvolatile ferroelectric memory device, and more particularly, to a nonvolatile ferroelectric memory device, in which four or more data levels are stored in one memory cell to obtain a multi-bit, and a method for driving the nonvolatile ferroelectric memory device.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to that of a dynamic random access memory (DRAM) and retains data even when power is off. For this reason, the nonvolatile ferroelectric memory has attracted considerable attention as a next generation memory device.
The FRAM and DRAM have similar structures as memory devices, but the FRAM includes a ferroelectric capacitor characterized by its high residual polarization.
Such a ferroelectric capacitor with the high residual polarization allows data to be maintained even if an electric field is removed.
FIG. 1 shows a hysteresis loop of a conventional ferroelectric.
As shown in FIG. 1, even if polarization induced by an electric field has the electric field removed, data is maintained at a certain amount (i.e., xe2x80x9cdxe2x80x9d and xe2x80x9caxe2x80x9d states) without being erased due to the presence of residual polarization (or spontaneous polarization).
A nonvolatile ferroelectric memory cell is used as a memory device such that the xe2x80x9cdxe2x80x9d and xe2x80x9caxe2x80x9d states correspond to 1 and 0, respectively.
FIG. 2 illustrates a schematic view of a unit cell according to a conventional nonvolatile ferroelectric memory.
As shown in FIG. 2, a bit line B/L is formed in one direction, and a wordline W/L is formed in a direction crossing the bit line B/L. A plate line P/L is spaced apart from the wordline W/L in a parallel direction with the wordline W/L. A transistor T1 has a gate connected with the wordline W/L and a source connected with the bit line B/L. A ferroelectric capacitor FC1 has its first terminal connected with a drain of the transistor T1 and its second terminal connected with the plate line P/L.
The data input/output operation of the conventional nonvolatile ferroelectric memory device will be explained.
FIG. 3A is a timing chart illustrating a write mode operation of the conventional ferroelectric memory, and FIG. 3B is a timing chart illustrating a read mode operation thereof.
In the write mode operation, as shown in FIG. 3A, an externally applied chip enable signal CSBpad is activated from a high level to a low level, and at the same time a write enable signal WEBpad is applied from a high level to a low level, thereby starting the write mode operation.
Subsequently, if address decoding starts in the write mode operation, a pulse applied to a corresponding wordline W/L is transited from a low level to a high level to select cells.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line P/L in a period where the wordline W/L is maintained at the high level.
To write a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in the selected cell, a high signal or a low signal synchoronized with the write enable signal WEBpad is applied to a corresponding bitline B/L.
In other words, a high signal is applied to the bitline B/L, and if the low signal is applied to the plate line P/L in a period during which the signal applied to the wordline W/L is high, a logic value xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor FC1.
A low signal is applied to the bitline B/L, and if the signal applied to the plate line P/L is high, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor FC1.
An explanation will be given below as to the read mode operation, data of which is stored in a cell by the above-described write mode operation.
As shown in FIG. 3B, if an externally applied chip enable signal CSBpad is activated from a high level to a low level, all the bitlines become equipotential to a low voltage by an equalizer signal EQ before a corresponding wordline W/L is selected.
Then, the respective bitline B/L becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline W/L by the decoded address, so that a corresponding cell is selected.
The high signal is applied to the plate line P/L of the selected cell to destroy data corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the ferroelectric capacitor FC1.
At this time, if the logic value xe2x80x9c0xe2x80x9d is stored in the ferroelectric capacitor FC1, the corresponding data is not destroyed.
The destroyed data and the non-destroyed data are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
That is, if the data is destroyed, the xe2x80x9cdxe2x80x9d state is transited to a xe2x80x9cfxe2x80x9d state as shown in the hysteresis loop of FIG. 1. If the data is not destroyed, the xe2x80x9caxe2x80x9d state is transited to the xe2x80x9cfxe2x80x9d state.
Thus, if the sensing amplifier is enabled after a set time elapses, the logic value xe2x80x9c1xe2x80x9d is output in the case where the data is destroyed, whereas the logic value xe2x80x9c0xe2x80x9d is output in the case where the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to its original data, the plate line P/L becomes inactive from the high level to the low level in a state in which the high signal is applied to the corresponding wordline.
However, the conventional nonvolatile ferroelectric memory cell has the following problems.
There is a limitation in reducing a chip size by storing data levels in all the cells. Also, there is a difficulty in obtaining the cost competitiveness of the chip.
Accordingly, the present invention is directed to a nonvolatile ferroelectric memory device and a method for driving the same that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a nonvolatile ferroelectric memory device and a method for driving the same in which a chip size is reduced and a chip has an enhanced cost competitiveness by replacing the conventional plurality of memory cells with one memory cell.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a nonvolatile ferroelectric memory device according to the present invention includes a first cell array block and a second cell array block, each divided into an upper part and a lower part; sensing amplifiers arranged one by one on multiple bit lines at a middle portion between the first cell array block and the second cell array block; a data I/O encoder connected to end portions of the multiple bit lines for outputting multi-bit signals by encoding outputs of the sensing amplifiers; and a first reference cell array block and a second reference cell array block arranged between the first cell array block and the data I/O encoder and between the second cell array block and the data I/O encoder.
In another aspect of the present invention, a method for driving a nonvolatile ferroelectric memory device having a bit line including one sub bit line and first, second, and third multiple bit lines, the method comprising the steps of selectively connecting the sub bit line to the first, second and third multiple bit lines by respectively connecting first, second, and third switching control blocks to the first, second and third multiple bit lines; activating the first, second and third switching control blocks by external controlling signals; connecting the sub bit line to a drain of a pull-down switching block; applying an external sub bit line pull-down signal to a gate of the pull-down switching block; applying is applied a signal for adjusting a power to the sub bit line to a source of the pull-down switching blocks; and storing cell data by applying a write voltage to the sub bit line from a low level to a high level.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.